Joerg-Neo900 | basically: you first place components, you solve conflicts during that. Then you start layouting the assumed most difficult parts with a best guess of layers you'll need. Pretty soon you'll notice if it can work or if you need an additional layer, or two | 00:04 |
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Joerg-Neo900 | ince you placed all components, there's actually no way you can't layout this design, given you have sufficient layers available | 00:05 |
Joerg-Neo900 | once* | 00:05 |
Joerg-Neo900 | and since this is a prototype, it wouldn't matter if we need 20 layers just to get something running. Optimization can happen later | 00:06 |
ravelo | Joerg-Neo900: thanks for explaining | 06:11 |
ravelo | Read it now | 06:11 |
Joerg-Neo900 | juts for correctness: there _are_ situations where you simply can't route stuff - when you need to connect 3 chips of 3*3cm each with traces none longer than 6mm - we don't have any such situation on Neo900 | 10:05 |
Joerg-Neo900 | at least not in proto_v2 | 10:06 |
DocScrutinizer05 | didn't know I got an alter ego out there: http://www.aptosid.com/index.php?name=PNphpBB2&file=viewtopic&p=18161&sid=ea75004f3c8edfb5154546e87e64f1e6#18161 | 12:01 |
DocScrutinizer05 | I'm afraid my experience will be exactly the same | 12:03 |
Joerg-Neo900 | I wonder how >>an sd card holder on the other side of BoB<< is a problem for placing connectors | 12:25 |
Joerg-Neo900 | I mean, neither the B2B conns nor the uSD holder are through-hole components | 12:26 |
Joerg-Neo900 | btw regarding layers needed, we discussed this quite a while ago already, with one of our prospect layouters that then failed to pick up on the task. Seeing the density (ratio of footprints area vs total available area) being very high, they assumed we might need 5 layers instead of 4 for LOWER | 12:39 |
Joerg-Neo900 | actually 6 layers | 12:40 |
Joerg-Neo900 | as a general rule, layouters should start with overprovisioning of layers and try to use as few layers as possible during routing. Then eventually you see how many layers you really need, maybe redo a few details that have a peak in layers needed to reduce layer count there, and as a final step you simply delete the unused layers from PCB config | 12:43 |
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